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1 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice cmos and ttl compatible i/o automatic page write operation: ?1 to 64 bytes in 10ms ?page load timer end of write detection: ?toggle bit ? data data data data data polling hardware and software write protection 100,000 program/erase cycles 100 year data retention features 3.0v to 3.6v supply read access times: 200/250/300 ns low power cmos dissipation: ?active: 15 ma max. ?standby: 150 a max. simple write operation: ?on-chip address and data latches ?self-timed write cycle with auto-clear fast write cycle time: ?10ms max. commercial, industrial and automotive temperature ranges description the cat28lv256 is a fast, low power, low voltage cmos parallel e 2 prom organized as 32k x 8-bits. it requires a simple interface for in-system programming. on-chip address and data latches, self-timed write cycle with auto-clear and v cc power up/down write protection eliminate additional timing and protection hardware. data polling and toggle status bits signal the start and end of the self-timed write cycle. additionally, the cat28lv256 features hardware and software write protection. the cat28lv256 is manufactured using catalyst? advanced cmos floating gate technology. it is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. the device is available in jedec approved 28-pin dip, 28-pin tsop or 32-pin plcc packages. block diagram 28lv256 f01 addr. buffer & latches addr. buffer & latches inadvertent write protection control logic timer row decoder column decoder high voltage generator a 6 ? 14 ce oe we a 0 ? 5 i/o 0 ?/o 7 i/o buffers 32,768 x 8 e 2 prom array 64 byte page register v cc data polling and toggle bit 256k-bit cmos parallel eeprom cat28lv256
cat28lv256 2 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice plcc package (n, g) dip package (p, l) pin configuration tsop top view (8mm x 13.4mm) (h13) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 i/o 6 i/o 5 i/o 4 gnd i/o 2 a 1 a 2 v cc we a 8 a 9 a 11 oe a 7 a 6 a 5 a 4 a 3 a 10 i/o 7 a 12 16 15 ce i/o 3 i/o 1 i/o 0 a 0 a 13 a 14 i/o 2 v ss i/o 6 i/o 5 13 14 20 19 18 17 9 10 11 12 24 23 22 21 a 1 a 0 i/o 0 i/o 1 oe a 10 ce i/o 7 a 5 a 4 a 3 a 2 5 6 7 8 1 2 3 4 a 14 a 12 a 7 a 6 a 9 a 11 28 27 26 25 v cc we a 13 a 8 a 6 a 5 a 4 a 3 5 6 7 8 a 2 a 1 a 0 nc 9 10 11 12 i/o 0 13 a 8 a 9 a 11 nc 29 28 27 26 oe a 10 ce 25 24 23 22 i/o 7 21 i/o 1 i/o 2 v ss nc i/o 3 i/o 4 i/o 5 14 15 16 17 18 19 20 4321323130 a 7 a 12 a 14 nc v cc we a 13 i/o 4 i/o 3 16 15 i/o 6 top view pin functions pin name function pin name function a 0 ? 14 address inputs we write enable i/o 0 ?/o 7 data inputs/outputs v cc 3.0 to 3.6 v supply ce chip enable v ss ground oe output enable nc no connect
cat28lv256 3 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice capacitance t a = 25 c, f = 1.0 mhz symbol test max. units conditions c i/o (1) input/output capacitance 10 pf v i/o = 0v c in (1) input capacitance 6 pf v in = 0v note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) the minimum dc input voltage is ?.5v. during transitions, inputs may undershoot to ?.0v for periods of less than 20 ns. ma ximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (3) output shorted for no more than one second. no more than one output shorted at a time. (4) latch-up protection is provided for stresses up to 100ma on address and data pins from ?v to v cc +1v. *comment stresses above those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specifica- tion is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. absolute maximum ratings* temperature under bias ................. ?5 c to +125 c storage temperature ....................... ?5 c to +150 c voltage on any pin with respect to ground (2) ........... ?.0v to +v cc + 2.0v v cc with respect to ground ............... ?.0v to +7.0v package power dissipation capability (ta = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (3) ........................ 100 ma reliability characteristics symbol parameter min. max. units test method n end (1) endurance 100,000 cycles/byte mil-std-883, test method 1033 t dr (1) data retention 100 years mil-std-883, test method 1008 v zap (1) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (1)(4) latch-up 100 ma jedec standard 17 mode selection mode ce we oe i/o power read l h l d out active byte write (we controlled) l h d in active byte write (ce controlled) l h d in active standby, and write inhibit h x x high-z standby read and write inhibit x h h high-z active
cat28lv256 4 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice d.c. operating characteristics v cc = 3.0v to 3.6v, unless otherwise specified limits symbol parameter min. typ. max. units test conditions i cc v cc current (operating, ttl) 15 ma ce = oe = v il , f = 1/t rc min, all i/o? open i sbc (2) v cc current (standby, cmos) 150 a ce = v ihc , all i/o? open i li input leakage current ? 1 av in = gnd to v cc i lo output leakage current ? 5 av out = gnd to v cc , ce = v ih v ih (2) high level input voltage 2 v cc +0.3 v v il low level input voltage ?.3 0.6 v v oh high level output voltage 2 v i oh = ?00 a v ol low level output voltage 0.3 v i ol = 1.0ma v wi write inhibit voltage 2 v a.c. characteristics, read cycle v cc = 3.0v to 3.6v, unless otherwise specified 28lv256-20 28lv256-25 28lv256-30 symbol parameter min. max. min. max. min. max. units t rc read cycle time 200 250 300 ns t ce ce access time 200 250 300 ns t aa address access time 200 250 300 ns t oe oe access time 80 100 110 ns t lz (1) ce low to active output 0 0 0 ns t olz (1) oe low to active output 0 0 0 ns t hz (1)(3) ce high to high-z output 50 55 60 ns t ohz (1)(3) oe high to high-z output 50 55 60 ns t oh (1) output hold from address change 0 0 0 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) v ihc = v cc ?.3v to v cc +0.3v. (3) output floating (high-z) is defined as the state when the external data line is no longer driven by the output buffer.
cat28lv256 5 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice a.c. characteristics, write cycle v cc = 3.0v to 3.6v, unless otherwise specified 28lv256-20 28lv256-25 28lv256-30 symbol parameter min. max. min. max. min. max. units t wc write cycle time 10 10 10 ms t as address setup time 0 0 0 ns t ah address hold time 100 100 100 ns t cs ce setup time 0 0 0 ns t ch ce hold time 0 0 0 ns t cw (3) ce pulse time 150 150 150 ns t oes oe setup time 0 0 0 ns t oeh oe hold time 0 0 0 ns t wp (3) we pulse width 150 150 150 ns t ds data setup time 50 50 50 ns t dh data hold time 0 0 0 ns t init (1) write inhibit period after power-up 5 10 5 10 5 10 ms t blc (1)(4) byte load cycle time 0.15 100 0.15 100 0.15 100 s v cc 1.8k c l = 100 pf c l includes jig capacitance 1.3k device under test output input pulse levels reference points 2.0 v 0.6 v v cc - 0.3v 0.0 v figure 1. a.c. testing input/output waveform (2) 28lv256 f04 note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) input rise and fall times (10% and 90%) < 10 ns. (3) a write pulse of less than 20ns duration will not initiate a write cycle. (4) a timer of duration t blc max. begins with every low to high transition of we . if allowed to time out, a page or byte write will begin; however a transition from high to low within t blc max. stops the timer. figure 2. a.c. testing load circuit (example) 28lv256 f05
cat28lv256 6 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice address ce oe we data out t as data in data valid high-z t cs t ah t ch t wc t oeh t blc t dh t ds t oes t wp address ce oe we t rc data out data valid data valid t ce t oe t oh t aa t ohz t hz v ih high-z t lz t olz device operation read data stored in the cat28lv256 is transferred to the data bus when we is held high, and both oe and ce are held low. the data bus is set to a high impedance state when either ce or oe goes high. this 2-line control architecture can be used to eliminate bus contention in a system environment. byte write a write cycle is executed when both ce and we are low, and oe is high. write cycles can be initiated using either we or ce , with the address input being latched on the falling edge of we or ce , whichever occurs last. data, conversely, is latched on the rising edge of we or ce , whichever occurs first. once initiated, a byte write cycle automatically erases the addressed byte and the new data is written within 10 ms. figure 3. read cycle 28lv256 f06 figure 4. byte write cycle [ we we we we we controlled] 28lv256 f07
cat28lv256 7 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice oe ce we address i/o t wp t blc byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 last byte t wc address ce oe we data out t as data in data valid high-z t ah t wc t oeh t dh t ds t oes t blc t ch t cs t cw page write the page write mode of the cat28lv256 (essentially an extended byte write mode) allows from 1 to 64 bytes of data to be programmed within a single e 2 prom write cycle. this effectively reduces the byte-write time by a factor of 64. following an initial write operation ( we pulsed low, for t wp , and then high) the page write mode can begin by issuing sequential we pulses, which load the address and data bytes into a 64 byte temporary buffer. the page address where data is to be written, specified by bits a 6 to a 14 , is latched on the last falling edge of we . each byte within the page is defined by address bits a 0 to a 5 (which can be loaded in any order) during the first and subsequent write cycles. each successive byte load cycle must begin within t blc max of the rising edge of the preceding we pulse. there is no page write window limitation as long as we is pulsed low within t blc max . upon completion of the page write sequence, we must stay high a minimum of t blc max for the internal auto- matic program cycle to commence. this programming cycle consists of an erase cycle, which erases any data that existed in each addressed cell, and a write cycle, which writes new data back into the cell. a page write will only write data to the locations that were addressed and will not rewrite the entire page. figure 5. byte write cycle [ ce ce ce ce ce controlled] 28lv256 f08 figure 6. page mode write cycle 28lv256 f09
cat28lv256 8 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice we ce oe i/o 6 t oeh t oe t oes t wc (1) (1) address ce we oe i/o 7 d in = x d out = x d out = x t oe t oeh t wc t oes data data data data data polling data polling is provided to indicate the completion of write cycle. once a byte write or page write cycle is initiated, attempting to read the last byte written will output the complement of that data on i/o 7 (i/o 0 ?/o 6 are indeterminate) until the programming cycle is com- plete. upon completion of the self-timed write cycle, all i/o? will output true data during a read cycle. toggle bit in addition to the data polling feature, the device can determine the completion of a write cycle, while a write cycle is in progress, by reading data from the device. this results in i/o 6 toggling between one and zero. once the write is complete, however, i/o 6 stops toggling and valid data can be read from the device. figure 7. data polling 28lv256 f10 figure 8. toggle bit 28lv256 f11 note: (1) beginning and ending state of i/o 6 is indeterminate.
cat28lv256 9 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice write data: aa address: 5555 write data: 55 address: 2aaa write data: 80 address: 5555 write data: aa address: 5555 write data: 55 address: 2aaa write data: 20 address: 5555 software data protection activated (1) write data: xx write last byte to last address to any address write data: aa address: 5555 write data: 55 address: 2aaa write data: a0 address: 5555 (4) noise pulses of less than 20 ns on the we or ce inputs will not result in a write cycle. software data protection the cat28lv256 features a software controlled data protection scheme which, once enabled, requires a data algorithm to be issued to the device before a write can be performed. the device is shipped from catalyst with the software protection not enabled (the cat28lv256 is in the standard operating mode). figure 9. write sequence for activating software data protection figure 10. write sequence for deactivating software data protection 28lv256 f12 28lv256 f13 note: (1) write protection is activated at this point whether or not any more writes are completed. writing to addresses must occur w ithin t blc max., after sdp activation. hardware data protection the following hardware data protection features are incorporated into the cat28lv256. (1) v cc sense provides write protection when v cc falls below 2.0v min. (2) a power on delay mechanism, t init (see ac charac- teristics), provides a 5 to 10 ms delay before a write sequence, after v cc has reached 2.4v min. (3) write inhibit is activated by holding any one of oe low, ce high, or we high.
cat28lv256 10 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice ce we aa 5555 55 2aaa data address t wc 80 5555 aa 5555 55 2aaa 20 5555 sdp reset device unprotected ce we t wp aa 5555 55 2aaa a0 5555 data address t blc t wc byte or page writes enabled to activate the software data protection, the device must be sent three write commands to specific addresses with specific data (figure 9). this sequence of commands (along with subsequent writes) must adhere to the page write timing specifications (figure 11). once this is done, all subsequent byte or page writes to the device must be preceded by this same set of write commands. the data protection mechanism is activated until a deactivate sequence is issued, regardless of power on/off transi- tions. this gives the user added inadvertent write pro- tection on power-up in addition to the hardware protec- tion provided. to allow the user the ability to program the device with an e 2 prom programmer (or for testing purposes) there is a software command sequence for deactivating the data protection. the six step algorithm (figure 10) will reset the internal protection circuitry, and the device will return to standard operating mode (figure 12 provides reset timing). after the sixth byte of this reset sequence has been issued, standard byte or page writing can commence. figure 11. software data protection timing figure 12. resetting software data protection timing
cat28lv256 11 doc. no. md-1071, rev. d ?2008 scillc. all rights reserved. characteristics subject to change without notice prefix device # suffix 28lv256 product number cat optional company id ni t tape & reel t: 500/reel package p: pdip n: plcc -25 temperature range blank = commercial (0 ? c to +70 ? c) i = industrial (-40 ? c to +85 ? c) a = automotive (-40 ? to +105 ? c) speed 25: 250ns 30: 300ns 20: 200ns* e = extended (-40 ? c to +125 ? c) l: pdip (lead free, halogen free) g: plcc (lead free, halogen free) h13: tsop (lead free, halogen free) ordering information notes: (1) the device used in the above example is a cat28lv256ni-25t (100,000 cycle endurance, plcc, industrial temperature, 250 ns access time, tape & reel). * commercial and industrial temperature range only.
cat28lv256 12 doc. no. md-1071, rev. d ? 2008 scillc. all rights reserved. characteristics subject to change without notice revision history date revision description 03-feb-04 a assigned doc number updated ordering info 27-feb-04 b added green packages 15-oct-08 c eliminate tsop (8mm x 13.4mm) snpb package. 18-nov-08 d change logo and fine print to on semiconductor

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